Instrukcja obsługi Microchip SY56023R
Microchip
nieskategoryzowany
SY56023R
Przeczytaj poniżej 📖 instrukcję obsługi w języku polskim dla Microchip SY56023R (12 stron) w kategorii nieskategoryzowany. Ta instrukcja była pomocna dla 38 osób i została oceniona przez 19.5 użytkowników na średnio 4.3 gwiazdek
Strona 1/12
SY56023R
Low Voltage 1.2V/1.8V/2.5V CML 2x2
Crosspoint Switch 6.4Gbps with
Equalization
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944 0800 • fax + 1 (408) 474 1000 • - - http://www.micrel.com
March 1, 2013
Revision 2.1
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY56023R is a fully-differential, low-voltage
1.2V/1.8V/2.5V CML 2x2 crosspoint switch with input
equalization. The SY56023R can process clock signals
as fast as 5GHz or data patterns up to 6.4Gbps.
The differential input includes Micrel’s unique, 3 pin input -
termination architecture that interfaces to CML differential
signals, without any level-shifting or termination resistor
networks in the signal path. The differential input can also
accept AC coupled LVPECL and LVDS signals. I- nput
voltages as small as 200mV (400mVPP) are applied
before the 9”, 18” or 27” FR4 transmission line. For AC-
coupled input interface applications, an internal voltage
reference is provided to bias the VT pin. The outputs are
CML, with extremely fast rise/fall times guaranteed to be
less than 80ps.
The SY56023R operates from a 2.5V ±5% core supply
and a 1.2V, 1.8V or 2.5V ±5% output supply and is
guaranteed over the full industrial temperature range
(– -40°C to +85°C). The SY56023R is part of Micrel’s high
speed, Precision Edge® product line.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge®
Features
•1.2V/1.8V/2.5V CML 2x2 crosspoint switch
•Equalizes 9, 18, 27 inches of FR4
•Guaranteed AC performance over temperature and
voltage:
– -DC to > 6.4Gbps Data throughput
– -DC to > 5GHz Clock throughput
– - -<280 ps propagation delay (IN to Q)
– <15 ps output skew
– <80 ps rise/fall times
•Ultra-low jitter design
– <1 psRMS - -cycle to cycle jitter
•High-speed CML outputs
•2.5V ±5% VCC , 1.2/1.8V/2.5V ±5% VCCO power supply
operation
•Industrial temperature range: –40°C to +85°C
•Available in 16-pin (3mm x 3mm) QFN package
Applications
•Data Distribution:
•SONET clock and data distribution
•Fiber Channel clock and data distribution
•Gigabit Ethernet clock and data distribution
Markets
•Storage
•ATE
•Test and measurement
•Enterprise networking equipment
•High-end servers
•Metro area network equipment
Micrel, Inc.
SY56023R
March 1, 2013
2 Revision 2.1
hbwhelp@micrel.com or (408) 955-1690
Ordering Information(1)
Part Number Package Type Operating Range Package Marking Lead Finish
SY56023RMG 16 -QFN Industrial R023 with Pb- Free
B -L Iar ine ndicator
NiPdAu
Pb- Free
SY56023RMGTR(2) - QFN 16 Industrial R023 with Pb- Free
B -L Iar ine ndicator
NiPdAu
Pb- Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Conguration
16-Pin QFN
Truth Table
SEL0 SEL1 Q0 Q1
L L IN0 IN0
L H IN0 IN1
H L IN1 IN0
H H IN1 IN1
EQ EQUALIZATION
LOW 27 “
FLOAT 18”
HIGH 9”
Micrel, Inc.
SY56023R
March 1, 2013
3 Revision 2.1
hbwhelp@micrel.com or (408) 955-1690
Pin Description
Pin Number Pin Name Pin Function
16,1
4,5
IN0, /IN0
IN1, /IN1
Differential Inputs: Signals as small as 200mV V
PK (400mVPP) applied to the input of 9, 18 or
27 inches 6 mil FR4 stripline transmission line are then terminated with the differential input.
Each input pin internally terminates with 50Ω to the VT pin.
2
3
VT0
VT1
Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin.
This pin provides a center-tap to a termination network for maximum interface flexibility. An
internal high impedance resistor divider biases VT to allow input AC coupling. For AC-
coupling, bypass VT with 0.1µF low-ESR capacitor to VCC. See “Interface Applications”
subsection and Figure 2a.
13 EQ Three level input for equalization control. High, float, low. EQ pin applies the same EQ
setting to both inputs.
15
6
SEL0
SEL1
These single ended TTL/CMOS compatible inputs, selects inputs IN0 or IN1. Note that - -
these inputs are internally connected to a 25kΩ pull-up resistor and will default to a logic
HIGH state if left open.
7 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the V
CC
pins as possible. Supplies input and core circuitry.
8 O VCC Output Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the V
CCO pins as
possible. Supplies the output buffers
14 GND,
Exposed adP
Ground: Exposed pad must be connected to a ground plane that is the same potential as the
ground pins.
12,11
10,9
Q0, /Q0
Q1, /Q1
CML Differential Output Pairs: Differential buffered copy of the input signal. The output swing
is typically 390mV. See “Interface Applications” subsection for termination information.
Specyfikacje produktu
| Marka: | Microchip |
| Kategoria: | nieskategoryzowany |
| Model: | SY56023R |
Potrzebujesz pomocy?
Jeśli potrzebujesz pomocy z Microchip SY56023R, zadaj pytanie poniżej, a inni użytkownicy Ci odpowiedzą
Instrukcje nieskategoryzowany Microchip
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
5 Lipca 2024
Instrukcje nieskategoryzowany
- nieskategoryzowany Perkins
- nieskategoryzowany SureFire
- nieskategoryzowany Cisco
- nieskategoryzowany IFM
- nieskategoryzowany NordicTrack
- nieskategoryzowany Kärcher
- nieskategoryzowany Lewitt
- nieskategoryzowany Vertiv
- nieskategoryzowany Celestron
- nieskategoryzowany Tripp Lite
- nieskategoryzowany Dometic
- nieskategoryzowany Motorola
- nieskategoryzowany TOGU
- nieskategoryzowany Wolfcraft
- nieskategoryzowany Betty Bossi
Najnowsze instrukcje dla nieskategoryzowany
28 Października 2024
28 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024
27 Października 2024