Instrukcja obsΕugi Texas Instruments SN74221N
Texas Instruments
Niesklasyfikowane
SN74221N
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SDLS213B β DECEMBER 1983 β REVISED NOVEMBER 2004
1
POST OFFICE BOX 655303 β’ DALLAS, TEXAS 75265
DDual Versions of Highly Stable SN54121
and SN74121 One Shots
DSN54221 and SN74221 Demonstrate
Electrical and Switching Characteristics
That Are Virtually Identical to the SN54121
and SN74121 One Shots
DPinout Is Identical to the SN54123,
SN74123, SN54LS123, and SN74LS123
DOverriding Clear Terminates Output Pulse
TYPE
MAXIMUM
OUTPUT
PULSE
LENGTH(S)
SN54221 21
SN74221 28
SN54LS221 49
SN74LS221 70
description/ordering information
The β221 and βLS221 devices are dual
multivibrators with performance characteristics
virtually identical to those of the β121 devices.
Each multivibrator features a negative-transition-
triggered input and a positive-transition-triggered
input, either of which can be used as an inhibit
input.
ORDERING INFORMATION
TAPACKAGEβ ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP N
T b
SN74221N SN74221N
PDIP β N Tube SN74LS221N SN74LS221N
0 CΒ°C t 70Β°
SOIC D
Tube SN74LS221D
LS221
0 CΒ°C to 70Β°SOIC β D Tape and reel SN74LS221DR LS221
SOP β NS Tape and reel SN74LS221NSR 74LS221
SSOP β DB Tape and reel SN74LS221DBR LS221
CDIP J
Tube
SNJ54221J SNJ54221J
β55Β° Β°C to 125 C CDIP β J Tube SNJ54LS221J SNJ54LS221J
55 CC to 125
LCCC β FK Tube SNJ54LS221FK SNJ54LS221FK
β Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright  2004, Texas Instruments Incorporated
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3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
1Cext
1Q
NC
2Q
2CLR
1CLR
1Q
NC
2Q
2Cext
1B
1A
NC
2A
2B
V
1R
ext
GND
NC
1A
1B
1CLR
1Q
2Q
2Cext
2Rext
/Cext
GND
VCC
1Rext/Cext
1Cext
1Q
2Q
2CLR
2B
2A
SN54221, SN54LS221 . . . J PACKAGE
SN74221 . . . N PACKAGE
SN74LS221 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
SN54LS221 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
ext/Cext
2R /Cext
NC β No internal connection
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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SDLS213B β DECEMBER 1983 β REVISED NOVEMBER 2004
2POST OFFICE BOX 655303 β’ DALLAS, TEXAS 75265
description/ordering information (continued)
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with
transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high
immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration
relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing
appropriate timing components. With Rext = 2 k⦠and Cext = 0, an output pulse typically of 30 ns is achieved
that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent
of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics
waveforms.
Pulse-width stability is achieved through internal compensation and is virtually independent of V CC and
temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing
capacitance (10 pF to 10 ¡F) and more than one decade of timing resistance (2 k⦠to 30 k⦠for the SN54221,
2 k⦠to 40 k to 70 k⦠for the SN74221, 2 k⦠⦠for the SN54LS221, and 2 k⦠to 100 k⦠for the SN74LS221).
Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 β 0.7 CextRext. In
circuits where pulse cutoff is not critical, timing capacitance up to 1000 Β΅F and timing resistance as low as 1.4 kβ¦
can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air
temperature is 25Β°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher
duty cycles are available if a certain amount of pulse-width jitter is allowed.
The variance in output pulse width from device to device typically is less than Β±0.5% for given external timing
components. An example of this distribution for the β221 is shown in Figure 3. Variations in output pulse width
versus supply voltage and temperature for the β221 are shown in Figures 4 and 5, respectively.
Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123
so that the β221 or βLS221 devices can be substituted for those products in systems not using the retrigger by
merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.
FUNCTION TABLE
(each monostable multivibrator)
INPUTS OUTPUTS
CLR A B Q Q
L X X L H
X HH X L
X HX L L
H L ββ β
H Hββ β
ββ‘L H β β
β Pulsed-output patterns are tested during
AC switching at 25Β°C with R
ext = 2 kβ¦, and
Cext = 80 pF.
β‘This condition is true only if the output of
the latch formed by the two NAND gates
has been conditioned to the logic 1 state
prior to CLR going high. This latch is
conditioned by taking either A high or
B low while CLR is inactive (high).
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SDLS213B β DECEMBER 1983 β REVISED NOVEMBER 2004
3
POST OFFICE BOX 655303 β’ DALLAS, TEXAS 75265
timing component connections
VCC
Rext
To Cext
Terminal
To Rext/Cext
Terminal
NOTE: Due to the internal circuit, the R
ext/Cext terminal never is more positive than the C
ext terminal.
Specyfikacje produktu
| Marka: | Texas Instruments |
| Kategoria: | Niesklasyfikowane |
| Model: | SN74221N |
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