Instrukcja obsล‚ugi Texas Instruments SN74AS573AN


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๎˜๎˜‚๎˜ƒ๎˜„๎˜…๎˜†๎˜๎˜ƒ๎˜‡๎˜ˆ๎˜‰๎˜Š๎˜‹๎˜๎˜‚๎˜ƒ๎˜„๎˜…๎˜๎˜ƒ๎˜‡๎˜ˆ๎˜…๎˜Š๎˜‹๎˜๎˜‚๎˜‡๎˜„๎˜…๎˜†๎˜๎˜ƒ๎˜‡๎˜ˆ๎˜‰๎˜Š๎˜‹๎˜๎˜‚๎˜‡๎˜„๎˜…๎˜๎˜ƒ๎˜‡๎˜ˆ๎˜…
๎˜Œ๎˜‰๎˜๎˜…๎˜†๎˜‹๎˜Ž๎˜๎˜๎˜๎˜‘๎˜’๎˜‹๎˜๎˜“๎˜…๎˜‚๎˜๎˜‘๎˜…๎˜“๎˜’๎˜‚๎˜๎˜‹๎˜†๎˜…๎˜๎˜‰๎˜”๎˜’๎˜
๎˜•๎˜–๎˜๎˜”๎˜‹๎˜ˆ๎˜๎˜๎˜๎˜…๎˜๎˜’๎˜‹๎˜Œ๎˜—๎˜๎˜‘๎˜—๎˜๎˜
SDAS048D โˆ’ DECEMBER 1989 โˆ’ REVISED JANUARY 1995
Copyright ๏ฃฉ 1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 โ€ข DALLAS, TEXAS 75265
POST OFFICE BOX 1443 โ€ข HOUSTON, TEXAS 77251โˆ’1443
โ€ข3-State Bu๎€er-Type Outputs Drive Bus
Lines Directly
โ€ขBus-Structured Pinout
โ€ขTrue Logic Outputs
โ€ขPackage Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), Standard Plastic (N) and
Ceramic (J) 300-mil DIPs, and Ceramic Flat
(W) Packages
description
These octal D-type transparent latches feature
3-state outputs designed speci๎‹ˆcally for driving
highly capacitive or relatively low-impedance
loads. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, outputs
(Q) respond to the data (D) inputs. When LE is low,
the outputs are latched to retain the data that was
set up.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low) or a high-impedance state. In
the high-impedance state, the outputs neither load
nor drive the bus lines signi๎‹ˆcantly. The
high-impedance state and the increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE does not a๎€ect internal operation of the
latches. Old data can be retained or new data can
be entered while the outputs are in the
high-impedance state.
The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range
of โˆ’55ยฐ ยฐ ยฐ ยฐC to 125 C. The SN74ALS573C and SN74AS573A are characterized for operation from 0 C to 70 C.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE LE D
OUTPUT
Q
L H H H
L H L L
L L X Q0
H X X Z
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
SN54ALS573C, SN54AS573A . . . J OR W PACKAGE
SN74ALS573C, SN74AS573A . . . DW OR N PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
SN54ALS573C, SN54AS573A . . . FK PACKAGE
(TOP VIEW)
2D
1D
OE
8Q
7Q 1Q
8D
G
ND
LE
V
CC
๎˜‘๎˜“๎˜Œ๎˜Ž๎˜—๎˜‰๎˜๎˜–๎˜Œ๎˜‚ ๎˜Ž๎˜…๎˜๎˜… ๎˜˜๎˜™๎˜š๎˜›๎˜œ๎˜๎˜ž๎˜Ÿ๎˜˜๎˜›๎˜™ ๎˜˜! "#๎˜œ๎˜œ$๎˜™๎˜Ÿ ๎˜ž! ๎˜›๎˜š %#&'๎˜˜"๎˜ž๎˜Ÿ๎˜˜๎˜›๎˜™ (๎˜ž๎˜Ÿ$)
๎˜‘๎˜œ๎˜›(#"๎˜Ÿ! "๎˜›๎˜™๎˜š๎˜›๎˜œ๎˜ ๎˜Ÿ๎˜› !%$"๎˜˜๎˜š๎˜˜"๎˜ž๎˜Ÿ๎˜˜๎˜›๎˜™! %$๎˜œ ๎˜Ÿ*$ ๎˜Ÿ$๎˜œ๎˜! ๎˜›๎˜š ๎˜$+๎˜ž! ๎˜–๎˜™!๎˜Ÿ๎˜œ#๎˜$๎˜™๎˜Ÿ!
!๎˜Ÿ๎˜ž๎˜™(๎˜ž๎˜œ( ,๎˜ž๎˜œ๎˜œ๎˜ž๎˜™๎˜Ÿ-) ๎˜‘๎˜œ๎˜›(#"๎˜Ÿ๎˜˜๎˜›๎˜™ %๎˜œ๎˜›"$!!๎˜˜๎˜™. (๎˜›$! ๎˜™๎˜›๎˜Ÿ ๎˜™$"$!!๎˜ž๎˜œ๎˜˜'- ๎˜˜๎˜™"'#($
๎˜Ÿ$!๎˜Ÿ๎˜˜๎˜™. ๎˜›๎˜š ๎˜ž'' %๎˜ž๎˜œ๎˜ž๎˜$๎˜Ÿ$๎˜œ!)


Specyfikacje produktu

Marka: Texas Instruments
Kategoria: Niesklasyfikowane
Model: SN74AS573AN

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