Instrukcja obsługi Texas Instruments SN74AUP1G17DCKR


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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AUP1G17
SCES579J – JUNE 2004 – REVISED SEPTEMBER 2017
SN74AUP1G17 Low-Power Single Schmitt-Trigger Buer
1
1 Features
1
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
2000-V Human-Body Model
(A114-B, Class II)
1000-V Charged-Device Model (C101)
Available in the Texas Instruments NanoStar™
Package
Low Static-Power Consumption
(ICC = 0.9 µA Maximum)
Low Dynamic-Power Consumption
(Cpd = 4.4 pF Typical at 3.3 V)
Low Input Capacitance (Ci= 1.5 pF Typical)
Low Noise – Overshoot and Undershoot
<10% of VCC
• Io Supports Partial-Power-Down Mode Operation
Includes Schmitt-Trigger Inputs
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
• tpd = 5.1 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
2 Applications
Grid Infrastructure
PC & Notebooks
• Tablets
Factory Automation & Control
• Gaming
• Server
3 Description
The AUP family of devices is TI's premier solution to
the industry's low-power needs in battery-powered
portable applications. This family ensures a very low
static- and dynamic-power consumption across the
entire VCC range of 0.8 V to 3.6 V, resulting in
increased battery life. This product also maintains
excellent signal integrity (see AUP – The Lowest-
Power Family Excellent Signal Integrityand ).
This device functions as an independent gate with
Schmitt-trigger inputs, which allows for slow input
transition and better switching-noise immunity at the
input.
NanoStar™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specied for partial-power-down
applications using Io. The Io circuitry disables the
outputs when the device is powered down. This
inhibits current backow into the device which
prevents damage to the device.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74AUP1G17DBV SOT-23 (5) 1.60 mm × 2.90 mm
SN74AUP1G17DCK SC70 (5) 1.25 mm × 2.00 mm
SN74AUP1G17DRL SOT-5X3 (5) 1.60 mm × 1.20 mm
SN74AUP1G17DRY SON (6) 1.00 mm × 1.45 mm
SN74AUP1G17DSF SON (6) 1.00 mm × 1.00 mm
SN74AUP1G17YFP DSBGA (4) 0.76 mm × 0.76 mm
SN74AUP1G17YZP DSBGA (5) 0.89 mm × 1.39 mm
SN74AUP1G17DPW X2SON (5) 0.80 mm × 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
(DBV, DCK, DPW, DRL, DRT, DRY, and YZP
Packages)
Logic Diagram (Positive Logic)
(YFP Package)


Specyfikacje produktu

Marka: Texas Instruments
Kategoria: Niesklasyfikowane
Model: SN74AUP1G17DCKR

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