Instrukcja obsługi Texas Instruments SN74AVC2T45DCTT

Przeczytaj poniżej 📖 instrukcję obsługi w języku polskim dla Texas Instruments SN74AVC2T45DCTT (32 stron) w kategorii Niesklasyfikowane. Ta instrukcja była pomocna dla 16 osób i została oceniona przez 8 użytkowników na średnio 5.0 gwiazdek

B1

DIR 5

7

A1 2

VCCA VCCB

B2

6

A2 3

18

VCCA VCCB

GND4

VCCA VCCB

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Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property mattersand other important disclaimers. PRODUCTION DATA.

SN74AVC2T45

SCES531L–DECEMBER 2003–REVISED MAY 2017

SN74AVC2T45 2-Bit, Dual Supply, Bus Transceiver

WithCongurable Level-Shifting and Translation

1

1 Features

1

•Availablein the TexasInstruments NanoFree™

Package

• VCC Isolation Feature:If EitherVCC Input Is at

GND,Both PortsAre inthe High-ImpedanceState

•Dual SupplyRail Design

•I/Os Are4.6-V OverVoltage Tolerant

• Io Supports Partial-Power-Down Mode Operation

•Max Data Rates

–500 Mbps(1.8 Vto 3.3V)

–320 Mbps(<1.8 Vto 3.3V )

–320 Mbps(Level-Shifting to2.5 Vor 1.8V)

–280 Mbps(Level-Shifting to1.5 V)

–240 Mbps(Level-Shifting to1.2 V)

•Latch-UpPerformance Exceeds100 mAPer

JESD 78,Class II

•ESD Protection Exceeds JESD22

2 Applications

• Smartphones

• Servers

•Desktop PCsand Notebooks

•Other PortableDevices

3 Description

This 2-bit non-inverting bus transceiver uses two

separate congurable power-supplyrails.The Aports

aredesigned to trackVCCA and acceptsany supply

voltage from1.2 V to 3.6V. The B portsare designed

to trackVCCB and acceptsany supplyvoltage from

1.2Vto 3.6 V.Thisallows foruniversallow-voltage

bidirectional translation and level-shifting between

any of the1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V

voltage nodes.

TheSN74AVC2T45 is designedfor asynchronous

communication between two databuses. Thelogic

levelsof thedirection-control(DIRpin) inputactivate

either theB-port outputs or theA-port outputs. The

device transmits datafrom the Abus to the Bbus

when the B-portoutputs are activatedand from the B

bus to the A bus when the A-port outputs are

activated. The input circuitryon both A and Bports

always is active and must have a logic HIGH or LOW

level applied to preventexcessleakage current on

the internalCMOS structure.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)

SN74AVC2T45DCTSM8 (8)2.95 mm× 2.80 mm

SN74AVC2T45DCUVSSOP (8)2.30 mm× 2.00 mm

SN74AVC2T45YZPDSBGA (8)1.89 mm× 0.89 mm

(1)For all available packages,see the orderableaddendumat

the end of the data sheet.

Logic Diagram(Positive Logic)

(1)Pin numbers are for the DCT and DCU packages only.

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