Instrukcja obsługi Texas Instruments SN74LVTH16501DL

Texas Instruments Niesklasyfikowane SN74LVTH16501DL

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 

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  

SCBS700F − JULY 1997 − REVISED AUGUST 2009

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DMembers of the Texas Instruments

Widebus Family

DUBT  Transceiver Combines D-Type

Latches and D-Type Flip-Flops for

Operation in Transparent, Latched, or

Clocked Mode

DState-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

DSupport Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

DSupport Unregulated Battery Operation

Down to 2.7 V

DTypical VOLP (Output Ground Bounce)

<0.8 V at VCC = 3.3 V, TA = 25°C

DIoff and Power-Up 3-State Support Hot

Insertion

DBus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

DDistributed VCC and GND Pins Minimize

High-Speed Switching Noise

DFlow-Through Architecture Optimizes PCB

Layout

DLatch-Up Performance Exceeds 500 mA Per

JESD 17

DESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

The ’LVTH16501 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) V CC operation,

but with the capability to provide a TTL interface to a 5-V system environment.

ORDERING INFORMATION

TAPACKAGE†ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SSOP DL

Tube SN74LVTH16501DL

LVTH16501

−40° °C to 85 C SSOP − DL Tape and reel SN74LVTH16501DLR LVTH16501

40 CC to 85

TSSOP − DGG Tape and reel SN74LVTH16501DGGR LVTH16501

−55° °C to 125 C Tube SNJ54LVTH16501WD SNJ54LVTH16501WDCFP − WD

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available

at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and UBT are trademarks of Texas Instruments.

SN54LVTH16501 . . . WD PACKAGE

SN74LVTH16501 . . . DGG OR DL PACKAGE

(TOP VIEW)

OEAB

LEAB

GND

VCC

GND

A10

A11

A12

GND

A13

A14

A15

VCC

A16

A17

GND

A18

OEBA

LEBA

GND

CLKAB

GND

VCC

GND

B10

B11

B12

GND

B13

B14

B15

VCC

B16

B17

GND

B18

CLKBA

GND

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  

SCBS700F − JULY 1997 − REVISED AUGUST 2009

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when

LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is

low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the

outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data ow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are

complementary (OEAB is active high and OEBA is active low).

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor

and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by

the current-sinking/current-sourcing capability of the driver.

These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

FUNCTION TABLE†

INPUTS

OUTPUT

OEAB LEAB CLKAB A

OUTPUT

L X X X Z

H H X L L

H H X H H

H L ↑L L

H L ↑H H

H L H X B0‡

H L L X B0§

†A-to-B data ow is shown; B-to-A ow is similar, but

uses OEBA, LEBA, and CLKBA.

‡Output level before the indicated steady-state input

conditions were established, provided that CLKAB

was high before LEAB went low

§Output level before the indicated steady-state input

conditions were established

 

     

  

SCBS700F − JULY 1997 − REVISED AUGUST 2009

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

CLK

OEAB

CLKAB

LEAB

LEBA

CLKBA

OEBA

354

To 17 Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †

Supply voltage range, VCC −0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high-impedance

or power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state, V O (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . .

Current into any output in the low state, IO: SN54LVTH16501 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74LVTH16501 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Current into any output in the high state, IO (see Note 2): SN54LVTH16501 48 mA. . . . . . . . . . . . . . . . . . . . .

SN74LVTH16501 64 mA. . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .